This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to the formation of capacitors in memory devices such as ferroelectric memories.
Conventional metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) logic and memory devices are prevalent in modern electronic devices and systems, as they provide an excellent combination of fast switching times and low power dissipation, along with their high density and suitability for large-scale integration. As is fundamental in the art, however, those devices are essentially volatile, in that logic and memory circuits constructed according to these technologies do not retain their data states upon removal of bias power. Especially in mobile and miniature systems, the ability to store memory and logic states in a non-volatile fashion is very desirable. As a result, various technologies for constructing non-volatile devices have been developed in recent years.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead-zirconium-titanate (PZT) or strontium-bismuth-tantalate (SBT), rather than silicon dioxide or silicon nitride as typically used in non-ferroelectric capacitors. Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits.
Non-volatile solid-state read/write random access memory (RAM) devices based on ferroelectric capacitors, such memory devices commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, have been implemented in many electronic systems, particularly portable electronic devices and systems. FRAMs are especially attractive in implantable medical devices, such as pacemakers and defibrillators. Various memory cell architectures including ferroelectric capacitors are known in the art, including the well-known 2T2C (two transistor, two capacitor) cells. Another type of FRAM cell is based on the well-known “6T” CMOS static RAM cell, which operates as an SRAM cell during normal operation, but in which ferroelectric capacitors coupled to each storage node can be programmed with the stored data state to preserve memory contents in non-volatile fashion. Ferroelectric capacitors are also implemented in some integrated circuits as programmable analog capacitors.
FIG. 1a illustrates the construction of an example of a portion of an integrated circuit including a portion of a ferroelectric random access memory (FRAM). In this example, ferroelectric capacitors 10 and metal-oxide-semiconductor (MOS) transistor 11 are disposed at or near a semiconducting surface of a semiconductor substrate, although capacitors 10 and transistor 11 may instead be formed at the surface of a semiconductor layer that overlies an insulator layer, such as according to a silicon-on-insulator (SOI) technology as known in the art. In the example of FIG. 1a, isolation dielectric structures 15, gate electrode 16, and n-type source/drain regions 14 are disposed at or near the surface of substrate 12, in the conventional manner for MOS integrated circuits. N-channel MOS transistor 11 in the example of FIG. 1a includes n-type source/drain regions 14 at the surface of p-type substrate 12 (or of a p-type “well” formed into substrate 12, as the case may be), with gate electrode 16 overlying a channel region between source/drain regions 14, and separated from the channel region by a gate dielectric 17 in the conventional manner. Interlevel dielectric 13 is disposed over transistor 11, with conductive plugs 18 disposed in a contact opening through interlevel dielectric 12 to provide a conductive connection between source/drain regions 14 of transistor 1a and overlying conductors and other structures, such as lower plates 20a of ferroelectric capacitors 10.
In the example of FIG. 1a, ferroelectric capacitor 10 is formed of a ferroelectric “sandwich” stack of conductive plates 20a, 20b, between which ferroelectric material 22 is disposed. Lower plates 20a of capacitors 10 are each formed at a location overlying conductive plug 18 so as to be in electrical contact with the underlying source/drain region 14 by way of that conductive plug 18. Conductive plates 20a, 20b are typically formed of the same conductive material or materials as one another, for purposes of symmetry, simplicity of the manufacturing flow, and improved ferroelectric polarization performance. As typical in many conventional implementations, conductive diffusion barrier layer 23a, for example of titanium-aluminum oxynitride (TiAlON), is disposed between lower plate 20a and conductive plug 18 and interlevel dielectric 13; a similar barrier layer (not shown) of the same material will also typically be in place above upper plate 20b. As mentioned above, a common material used as ferroelectric material 22 in this conventional capacitor 10 is lead-zirconium-titanate (PZT), deposited by way of metalorganic chemical vapor deposition. Ferroelectric material 22 in capacitor 10 is desirably as thin as practicable, for purposes of electrical performance (e.g., capacitance), and for consistency with the deep sub-micron features used to realize modern integrated circuits.
Lower conductive plate 20a and upper conductive plate 20b are formed from one or more layers of conductive metals, metal oxides, and the like. A typical construction of lower conductive plate 20a is a stack of a diffusion barrier layer in contact with conductive plug 18 and a layer of a noble metal (e.g., Ir, Ru, Pt, Rh, Pt, Pd, Au) or metal oxide (e.g., RuOx, IrOx, PdOx, SrRuO3) overlying the barrier layer and in contact with the ferroelectric material 22. As described in commonly assigned U.S. Pat. No. 6,656,748, incorporated herein by reference, in capacitors in which PZT serves as ferroelectric material 22, sputter deposited iridium (Ir) is a preferred material for the portion of lower conductive plate 20a that is in direct contact with the PZT. As mentioned above, upper conductive plate 20b is typically formed of the same materials as lower conductive plate 20a, deposited in the reverse order (e.g., with iridium in contact with the top surface of PZT ferroelectric material 22).
By way of background, U.S. Pat. No. 6,656,748, commonly assigned herewith and incorporated herein by reference, describes a method of forming an integrated circuit including ferroelectric capacitors. In particular, this Patent describes the formation ferroelectric capacitors including a “stack etch”, by way of which the upper and lower plates, and the PZT ferroelectric material therebetween, are etched using the same patterned mask element. The etch chemistry and process described in that Patent, as well as other conventional ferroelectric stack etches, result in a non-vertical sidewall profile for the structure, an example of which is shown in detail in FIG. 1b. As shown in that Figure, the sidewalls of upper and lower plates 20a, 20b, PZT ferroelectric material 22, and barrier layer 23a are at an angle φ relative to the horizontal; as known in the art, the sidewall angles of plates 20a, 20b and layer 23a may vary slightly from one another and from angle φ of ferroelectric material 22, considering the differences in their material properties, but the sidewall of the overall structure of capacitor 10 will generally follow the sidewall angle φ of ferroelectric material 22. The view of FIG. 1b also illustrates the presence of hard mask element 23b, typically formed of the same material as barrier layer 23a, following the stack etch. Hard mask element 23b defines the location and dimensions of upper plate 20a; as shown in FIG. 1b, hard mask element 23b tends to be etched back from its original dimensions 23b′ as barrier layer 23a is etched. In modern conventional implementations, angle φ is about 70°. (This angle φ as shown in FIGS. 1a and 1b is shallower than this typical 70° value to emphasize its effect, as will now be described.)
This non-vertical sidewall angle φ of conventional ferroelectric capacitors has been observed to limit the density of ferroelectric capacitors in integrated circuits. In this regard, FIG. 1a illustrates certain dimensions in the structure that determine the maximum density of structures in an array of ferroelectric capacitors 10. As known in the art, the capacitance of any capacitor is directly proportional to the area of its dielectric material. In the example of FIG. 1a, width WPZT of ferroelectric material 22 thus determines the capacitance of capacitors 10, which is constant over all capacitors 10 in a given array. Circuit requirements typically determine the minimum acceptable capacitance of capacitors 10, and thus determine the value of this width WPZT. Minimum distance Dcap between lower plates 20a of adjacent capacitors 10 is selected for the manufacturing technology to avoid capacitor-to-capacitor shorting; similarly, a minimum distance Dct between lower plates 20a and adjacent contact plugs 18 is selected to avoid capacitor-to-contact shorting. These minimum distances Dcap, Dct typically depend on the manufacturing and photolithography technology being used.
As evident from FIG. 1a, however, the non-vertical sidewall angle φ of the ferroelectric stack (i.e., barrier layer 23a, plates 20a, 20b, and ferroelectric material 22) affects the spacing of capacitors 10 from one another and from adjacent contacts. As-patterned hard mask elements 23b′ define the dimensions and placement of corresponding upper plates 20b. But in addition to the spacing between hard mask elements 23b′ of adjacent capacitors 10 (and capacitor 10 relative to an adjacent contact), the sidewall angle φ must be taken into account in order to maintain the necessary minimum distances Dcap, Dct. A shallower sidewall angle φ requires larger spacing between as-patterned hard mask elements 23b′ for adjacent capacitors 10, and between hard mask elements 23b′ and adjacent contact plugs 18, in order to maintain minimum distances Dcap, Dct for a given ferroelectric width WPZT. This layer spacing results in reduced density of ferroelectric capacitors 10 per unit chip area. Conversely, a steeper sidewall angle φ would allow closer spacing of as-patterned hard mask elements 23b′, attaining an increased ferroelectric capacitor density.
By way of further background, it is known that sidewall angles of a structure being etched can be steepened by performing a plasma etch under conditions of increased bias RF power applied to the electrode at which the semiconductor wafer is disposed.